ID installable LSI, secret key installation method, LSI test method, and LSI development method

ABSTRACT

In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.

BACKGROUND OF THE INVENTION

The present invention relates to a technology related to development,fabrication and test of LSIs in which an ID or a secret key has beeninstalled.

In general CMOS LSIs, it is difficult to install different keys.Because, key is implemented in General CMOS LSIs by hard-wired logic orROM. So, key is not able to changing. A key may be loaded from anexternal ROM. In this case, however, the key may be analyzed inside asystem. Also, a person other than the key administrator, such as anetwork distributor, an LSI designer and a set designer, may possiblycome to know the key. In addition, it is difficult to write keys withdifferent values by mass-production technology. The package may beunsealed for chip analysis. Moreover, there is no way to verify whetheror not the key has been installed correctly. That is, testing ofinternal keys is difficult.

SUMMARY OF THE INVENTION

An object of the present invention is providing LSIs permitting easyinstallation of various IDs.

Another object of the present invention is providing a secret keyinstallation method in which the concealment of the secret key in an LSIenhances or the setting of the value of the secret key to be installedis facilitated.

Yet another object of the present invention is providing an LSI testmethod enabling testing of the installed ID value without increase ofthe LSI circuit count.

Yet another object of the present invention is providing an LSIdevelopment method in which a sufficiently high degree of concealment ofthe secret key is ensured in the development process.

Specifically, the present invention is directed to an ID installable LSIincluding: a decoding section for receiving an ID signal representingthe ID from outside the LSI, decoding the ID signal, and outputting thedecoded signal; a value holding circuit for receiving the decodedsignal, writing the value represented by the decoded signal therein whenan operation setting signal is active, and holding the written valuewhen the operation setting signal is inactive; and an ID memory part forstoring the value held in the value holding circuit as the ID.

According to the invention described above, IDs of various values can beinstalled in LSIs only by changing the value of the ID signal. Thisenables mass production of ID-installed LSIs.

In another aspect, the present invention is directed to a method forinstalling a secret key in an LSI, including the step of bonding asecond LSI to a first LSI, wherein the first LSI comprises: a memorypart for storing a first secret key; first and second external inputterminals; a selector having an input for receiving the first secret keyand the other input connected with the first external input terminal,the selector also having a selection signal input connected with thesecond external input terminal; and a processing circuit using theoutput of the selector as a secret key, the second LSI includes: amemory part for storing a second secret key; a first external outputterminal from which the second secret key is output; and a secondexternal output terminal from which a selection signal is output, theselection signal being set so that the selector of the first LSI selectsand outputs the other input, and the step of bonding comprises bondingthe second LSI to the first LSI so that the first and second externaloutput terminals of the second LSI are connected to the first and secondexternal input terminals of the first LSI, respectively.

According to the invention described above, the second LSI with thesecond secret key installed therein is bonded to the first LSI. Thismakes it extremely difficult to monitor the second secret key outsidethe LSI, and thus improves the concealment of the second secret key.

Alternatively, the present invention is directed to a method forinstalling a secret key in an LSI, including the step of bonding asecond LSI to a first LSI, wherein the first LSI includes: first, secondand third external input terminals; a memory part for storing a firstsecret key and a first random number of seed and outputting either oneof the first secret key and the first random number of seed according toa signal input at the first external input terminal; a random numbergeneration circuit for receiving the output of the memory part and asignal input at the second external input terminal; a selector forreceiving the output of the memory part and the output of the randomnumber generation circuit as inputs and selecting and outputting eitherone of the inputs according to a signal input at the third externalinput terminal; and a processing circuit using the output of theselector as the secret key, the second LSI includes: a memory part forstoring a second random number of seed; a first external output terminalfrom which a selection signal is output, the selection signal being setso that the memory part of the first LSI outputs the first random numberof seed; a second external output terminal from which the second randomnumber of seed is output; and a third external output terminal fromwhich a selection signal is output, the selection signal being set sothat the selector of the first LSI selects and outputs the output of therandom number generation circuit, and the step of bonding includesbonding the second LSI to the first LSI so that the first, second andthird external output terminals of the second LSI are connected to thefirst, second and third external input terminals of the first LSI,respectively.

According to the invention described above, the second LSI with thesecond random number of seed installed therein is bonded to the firstLSI. This makes it extremely difficult to monitor the secret keygenerated based on the first and second random number of seed, and thusimproves the concealment of the secret key.

Alternatively, the present invention is directed to a method forinstalling a secret key in an LSI, including: a first step ofdetermining the position to be bumped in a pad portion of a second LSIaccording to the ID provided for a first LSI; a second step of bumpingthe position in the second LSI determined in the first step; and a thirdstep of bonding the bumped second LSI to the first LSI.

According to the invention described above, the ID value to be suppliedto the first LSI can be changed only by changing the position to bebumped in the second LSI.

Alternatively, the present invention is directed to a method forinstalling a secret key in an LSI, including: a first step of selectingone wiring LSI among a plurality of types of wiring LSIs; and a secondstep of bonding a first LSI and a second LSI to the wiring LSI selectedin the first step, wherein the wiring LSI includes one external inputterminal and a plurality of external output terminals, one of theplurality of external output terminals determined according to the typeof the wiring LSI being connected with the external input terminal, thefirst LSI including: a plurality of random number input terminals; and arandom number generation circuit connected with the random number inputterminals via different input lines for generating a random number to beused as a secret key based on random number data input via one of theinput lines with a type of logic unique to the used input line, thesecond LSI includes: a memory part for storing random number data; and arandom number output terminal for outputting the random number datastored in the memory part, and the second step comprises bonding thefirst LSI to the selected wiring LSI so that the random number inputterminals of the first LSI are connected to the corresponding externaloutput terminals of the wiring LSI, and bonding the second LSI to thewiring LSI so that the random number output terminal of the second LSIis connected to the external input terminal of the wiring LSI.

According to the invention described above, the input line via which therandom number data is input into the random number generation circuitcan be changed by changing the type of the wiring LSI. This enablesgeneration of mass-production secret keys with different types of logic.

According to yet another aspect, the present invention is directed to anLSI test method including the step of: testing an LSI with a tester LSI,the LSI having a memory part from which an ID value is output accordingto an address supplied, wherein the LSI comprises a first test circuit,the tester LSI comprises a second test circuit, the first and secondtest circuits, in the state of being connected with each other,outputting the same value as that output from the memory part whenreceiving the same address as that supplied to the memory part, and thestep of testing comprises connecting the second test circuit of thetester LSI to the first test circuit of the LSI and comparing the outputof the connected first and second test circuits with the output of thememory part.

According to the invention described above, the installed ID value canbe tested without increase of the LSI circuit count.

According to yet another aspect, the present invention is directed to anLSI development method including the steps of: a key publishergenerating a development secret key and a random number of seed andsupplying the development secret key and the random number of seed to afirst developer; the first developer developing a first LSI using thedevelopment secret key and the random number of seed; the key publishergenerating a random number and supplying the random number to a seconddeveloper; the second developer developing a second LSI using the randomnumber; the first developer supplying the developed first LSI to aproducer; the second developer supplying the developed second LSI to theproducer; the key publisher determining the position in which the firstLSI and the second LSI are bonded together and supplying the position tothe producer; and the producer bonding the first LSI and the second LSItogether according to the position of bonding supplied from the keypublisher.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an ID installable LSI of the firstembodiment of the present invention.

FIG. 2 illustrates a specific example of configuration of a decodingsection and a fuse circuit.

FIG. 3 is a view of a constituent of the fuse circuit.

FIG. 4 illustrates operations of the constituent of the fuse circuit.

FIG. 5 is a flowchart of a fabrication process of an encryption LSIusing the ID installable LSI.

FIG. 6 illustrates an example of an LSI in which a random numbergeneration circuit is added to the configuration of FIG. 1.

FIG. 7 illustrates a secret key installation method of the secondembodiment of the present invention.

FIG. 8 illustrates a secret key installation method of the thirdembodiment of the present invention.

FIGS. 9(a) to 9(c) illustrate the relationship between the position ofbonding of an ID LSI and the pad via which a second random number ofseed is input.

FIGS. 10(a) to 10(c) illustrate a secret key installation method of thefourth embodiment of the present invention.

FIG. 11 illustrates the result of execution of the fourth embodiment.

FIG. 12 illustrates a secret key installation method of the fifthembodiment of the present invention.

FIG. 13 illustrates the result of execution of the fifth embodiment.

FIG. 14 illustrates an LSI test method of the sixth embodiment of thepresent invention.

FIG. 15 illustrates another LSI test method of the sixth embodiment ofthe present invention.

FIG. 16 illustrates a specific example of configuration of a tester LSI.

FIG. 17 illustrates an encryption ID LSI of the seventh embodiment ofthe present invention.

FIG. 18 is a flowchart of a development method of the encryption ID LSIshown in FIG. 17.

FIG. 19 is a continuation of the flowchart of the development method ofthe encryption ID LSI shown in FIG. 17.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to the accompanying drawings.

First Embodiment

FIG. 1 is a block diagram of an ID installable LSI of the firstembodiment of the present invention. The LSI 10 shown in FIG. 1 isconfigured to be able to receive an ID as a secret key in itsfabrication process. In other words, signals Fuse and Fusedec aresupplied to the LSI 10 with a tester for shipment inspection, forexample. In this way, such LSIs 10 with IDs of different values can beeasily mass-produced.

A decoding section 11 receives the ID signal Fusedec representing an IDexternally and decodes the ID signal Fusedec. A fuse circuit 12,providing as a value holding circuit, receives the decoded signal outputfrom the decoding section 11 and writes the value represented by thedecoded signal therein when an operation setting signal Fuse is active.The written value is held when the operation setting signal Fuse isinactive. An ID RAM 13, providing as an ID memory part, stores the valueheld in the fuse circuit 12 as the ID.

FIG. 2 illustrates a specific example of configuration of the decodingsection 11 and the fuse circuit 12 shown in FIG. 1. The decoding section11 receives the ID signal Fusedec and a clock CLK and outputs a 3-bitdecoded signal Fusedec2. The fuse circuit 12 includes three fuse pairs121, 122 and 123 made of nonvolatile elements, to receive and hold the3-bit values of the decoded signal Fusedec2.

FIG. 3 illustrates one constituent of the fuse circuit 12 shown in FIG.2, which corresponds to 1-bit value and includes two fuses FUSEA andFUSEB.

The operation of the constituent of the fuse circuit 12 shown in FIG. 3will be described with reference to FIG. 4. First, as shown in FIG. 4(a) and (b), during write operation, the operation setting signal Fuseis set at “2” level (active). Under this setting, when the decodedsignal Fusedec2 is “0”, the fuse FUSEA is turned to the connected state(a), and when the decoded signal Fusedec2 is “1”, FUSEB is turned to theconnected state (b). After the write operation, as shown in FIG. 4 (c)and (d), the operation setting signal Fuse is set at “X” level. Underthis setting, the value “1” is held when the fuse FUSEA is in theconnected state (c), and the value “0” is held when the fuse FUSEB is inthe connected state (d), irrespective of the value of the decoded signalFusedec2. The “2” level may be 5V, the “1” level may be 3V, and the “X”level may be 0 or 3V, for example.

With the configuration described above, an ID of a different value canbe installed in the LSI 10 only by changing the value of the ID signalFusedec, and this enables mass production of LSIs in which different IDvalues have been installed. After the writing of the ID value and beforeshipment of the product, the terminal for the signal Fusedec is fixed at“1” in an LSI package, or the signal Fusedec itself is fixed at “1” witha fuse, so as to ensure that no change of the ID value is allowedexternally after shipment of the product. FIG. 5 shows an example of aflow of the fabrication process of an encryption LSI using such an IDinstallable LSI.

FIG. 6 illustrates an example of an LSI in which a random numbergeneration circuit 14 is provided in addition to the configuration ofFIG. 1. In the LSI 10A shown in FIG. 6, the random number generationcircuit 14 receives the value held in the fuse circuit 12 and generatesa random number based on the received value. The ID RAM 13 stores therandom number generated by the random number generation circuit 14 asthe ID), in place of the value held in the fuse circuit 12.

Any value holding circuit other than the fuse circuit 12 described abovemay be used as long as the circuit can fix a value and the setting ofthe fixed value can be made in the fabrication process. The fuse circuit12 may be a FPGA, a flash, a mask ROM or a fuse circuit involvingtrimming of a wiring layer with a laser ray. A register, for example,may be used in place of the ID RAM 13.

Second Embodiment

FIG. 7 illustrates a secret key installation method of the secondembodiment of the present invention. In this embodiment, as shown inFIG. 7, an ID LSI 22 as the second LSI is bonded to an encryption LSI 21as the first LSI, to thereby install a secret key for mass productionstored in the ID LSI 22 in the encryption LSI 21.

As shown in FIG. 7 (a), the encryption LSI 21 includes a ROM 211providing as a memory part storing a secret key for development as thefirst secret key, pads 212 and 213 as the first and second externalinput terminals, a selector 214, and an circuit 215 for encryption as aprocessing circuit using the output of the selector 214 as the secretkey. One input of the selector 214 receives the development secret keystored in the ROM 211, and the other input thereof is connected with thepads 212. The selector 214 is also connected with the pad 213. Theselector 214 selects and outputs the development secret key stored inthe ROM 211 when a selection signal received is “H”, and selects andoutputs a signal input at the pads 212 when the selection signal is “L”.In the encryption LSI 21, the pad 213 is in the internally pulled-upstate, to thereby allow the development secret key to be input into theencryption circuit 215 via the selector 214.

The ID LSI 22 includes a memory part 221 storing a secret key for massproduction as the second secret key, pads 222 as the first externaloutput terminal from which the mass-production secret key is output, anda pad 223 as the second external output terminal connected to the groundGND.

As shown in FIG. 7 (b), the ID LSI 22 is bonded to the encryption LSI 21so that the pads 222 and 223 of the ID LSI 22 are connected to the pads212 and 213 of the encryption LSI 21, respectively. As a result, theinput terminal of the selector 214 for receiving the selection signal isconnected to the ground GND via the pad 213 and the pad 223 of the IDLSI 22. By this connection, the selector 214 receives “L” as theselection signal, to thereby allow the mass-production secret keyinstalled in the ID LSI 22 to be input into the encryption circuit 215via the selector 214.

In this embodiment, the ID LSI 22 in which the mass-production secretkey has been installed is bonded to the encryption LSI 21. This makes itextremely difficult to monitor the mass-production secret key fromoutside the LSI, and thus improves the concealment of themass-production secret key.

Third Embodiment

FIG. 8 illustrates a secret key installation method of the thirdembodiment of the present invention. In FIG. 8, a first random number ofseed for generation of a mass-production secret key, as well as adevelopment secret key as the first secret key, are installed in asystem LSI 31 as the first LSI. An ID LSI 32 having a second randomnumber of seed for generation of the mass-production secret key isbonded to the system LSI 31. A random number generation circuit 313generates a value based on the first and second random number of seed,and the generated value is used as the mass-production secret key.

More specifically, as shown in FIG. 8, in the system LSI 31, a ROM 311as a memory part stores the development secret key and the first randomnumber of seed, and outputs either one of them according to a signalinput at a pad 312 as the first external input terminal. The randomnumber generation circuit 313 generates the mass-production secret keybased on the first random number of seed output from the ROM 311 and thesecond random number of seed input at pads 314 as the second externalinput terminal. A selector 316 selects and outputs either one of theoutput of the ROM 311 and the output of the random number generationcircuit 313 according to a signal input at a pad 315 as the thirdexternal input terminal. A verification section 317 as a processingcircuit uses the output of the selector 316 as the secret key.

The ROM 311 outputs the development secret key when the input signal atthe pad 312 is “H”, and outputs the first random number of seed when theinput signal is “L”. The selector 316 outputs the output of the ROM 311when the input signal at the pad 315 is “H”, and outputs the output ofthe random number generation circuit 313 when the input signal is “L”.Before the bonding of the ID LSI 32, both the pads 312 and 315 are in aninternally pulled-up state, to allow the output of the ROM 311, that is,the development secret key to be output from the selector 316.

The ID LSI 32 includes a memory part 321 storing the second randomnumber of seed, pads 322 as the first external output terminal connectedto the ground GND, pads 323 as the second external terminal foroutputting the second random number of seed stored in the memory part321, and pads 324 as the third external output terminal connected to theground GND.

The ID LSI 32 is bonded to the system LSI 31 so that the pads 322, 323and 324 of the ID LSI 32 are connected to the pads 312, 314 and 315 ofthe system LSI 31, respectively. By this connection, the signal of “L”is applied to both the pads 312 and 315 of the system LSI 31. Thus, themass-production secret key, generated by the random number generationcircuit 313 based on the first random number of seed stored in the ROM311 and the second random number of seed supplied to the pads 314, isinput into the verification section 317 via the selector 316.

In this embodiment, the ID LSI 32 in which the second random number ofseed has been installed is bonded to the system LSI 31. This makes itextremely difficult to monitor the mass-production secret key fromoutside the LSI, and thus improves the concealment of themass-production secret key.

In addition, in this embodiment, the value of the mass-production secretkey can be changed by changing the position of bonding of the ID LSI 32to the system LSI 31.

As shown in FIG. 8, the pads 314 include a plurality of terminals suchas three terminals as illustrated. The three terminals are connected tothe random number generation circuit 313 via different input lines 318a, 318 b and 318 c. The random number generation circuit 313 generates arandom number with a type of logic unique to each of the input lines 318a, 318 b and 318 c via which the signal is input. Also, the pads 323 ofthe ID LSI 32 for outputting the second random number of seed arearranged in three rows and three columns. Each column of the pads 323corresponds to each terminal of the pads 314 of the system LSI 31.

FIG. 9 illustrates the relationship between the connection between thepads 314 of the system LSI 31 and the pads 323 of the ID LSI 32 and thebonding position. In FIG. 9, the dashed-line rectangles B1, B2 and B3shown relative to the ID LSI 32 correspond to the dashed-line rectangleA of the system LSI 31 shown in FIG. 8. That is, when the position inFIG. 9 (a) is regarded as the reference, the ID LSI 32 is bonded in aposition displaced downward by one pad in FIG. 9 (b), and bonded in aposition displaced downward by two pads in FIG. 9 (c).

In the bonding shown in FIG. 9 (a) in which the bottom row of the pads323 of the ID LSI 32 are aligned with the pads 314 of the system LSI 31,the second random number of seed is input into the random numbergeneration circuit 313 via the input line 318 a. Likewise, in thebonding shown in FIG. 9 (b) in which the second row of the pads 323 arealigned with the pads 314 of the system LSI 31, the second random numberof seed is input into the random number generation circuit 313 via theinput line 318 b. In the bonding shown in FIG. 9 (c) in which the toprow of the pads 323 are aligned with the pads 314 of the system LSI 31,the second random number of seed is input into the random numbergeneration circuit 313 via the input line 318 c.

As described above, the input line via which the second random number ofseed is input into the random number generation circuit 313 can bechanged by changing the position of the bonding of the ID LSI 32.Therefore, the output of the random number generation circuit 313, thatis, the value of the mass-production secret key can be changed with theposition of the bonding of the ID LSI 32.

Fourth Embodiment

FIGS. 10 and 11 illustrate a secret key installation method of thefourth embodiment of the present invention. As shown in FIG. 10 (a), anencryption LSI 41 as the first LSI includes a circuit 411 of a ROMstructure and an encryption circuit 413 receiving an ID value outputfrom the circuit 411. The circuit 411 outputs the ID value according tothe power supplied (VDD or VSS) at pads 412. As shown in FIG. 10 (b), anID LSI 42 as the second LSI includes a plurality of pads 421 eachconnected to a power supply line VDD or VSS.

First, the positions of the pads of the ID LSI 42 that should be bumpedare determined according to the ID to be provided to the encryption LSI41. Assuming that the ID value is Fh and Ah (h represents thehexadecimal notation), the positions that are not enclosed with arectangle 422 in FIG. 10 (c) are determined as the positions to bebumped.

Thereafter, the determined positions of the ID LSI 42 are bumped, and asshown in FIG. 11, the bumped ID LSI 42 is bonded to the encryption LSI41. In this way, the power supplied (VDD or VSS) at the bumped positionsof the pads 421 is input into the encryption circuit 41 as the ID value.

As described above, in this embodiment, the ID value to be provided tothe encryption LSI can be changed only by changing the positions to bebumped in the ID LSI 42.

Fifth Embodiment

FIGS. 12 and 13 illustrate a secret key installation method of the fifthembodiment of the present invention. In this embodiment, a system LSI 51as the first LSI and a random number LSI 52 as the second LSI are bondedto a wiring LSI 53, for installation of a secret key. By selection of awiring LSI used for the bonding among a plurality of wiring LSIs, thelogic for generation of a random number in the system LSI is changed.

As shown in FIG. 12, in the system LSI 51 as the first LSI, a ROM 511stores a development secret key and a random number of seed, and outputsone of them according to a signal input at a pad 512. More specifically,when a selection signal sell input at the pad 512 is “H”, a selector 516outputs input A indicating “H” to thereby fix the most significant bitADDn of the address of the ROM 511 at “H”. Thus, only the address regionstoring the development secret key is made available. On the contrary,when the selection signal sell is “L”, the selector 516 outputs input Bindicating “L”, and thus only the address region storing the randomnumber of seed is made available.

A random number generation circuit 513 generates a random number to beused as a mass-production secret key based on the random number of seedoutput from the ROM 511 and random number data input via pads 514 as therandom number input terminal. A selector 517 selects and outputs eitherone of the output of the ROM 511 and the output of the random numbergeneration circuit 513. More specifically, the selector 517 outputsinput A, that is, the output of the ROM 511 when a selection signal sel2input at a pad 515 is “H”, and outputs input B, that is, the output ofthe random number generation circuit 513 when the selection signal sel2is “L”. A verification section 518 uses the output of the selector 517as the secret key.

The pads 512 and 515 are in the internally pulled-up state, and thusboth the selection signals sell and sel2 are “H”, to thereby allow theselector 517 to select and output the development secret key output fromthe ROM 511.

The random number LSI 52 includes a memory part 521 storing randomnumber data and a pad 522 as the random number output terminal foroutputting the random number data stored in the memory part 521.

The wiring LSI 53 includes a pad 531 as the external input terminal andpads 532 as the external output terminal. One of the pads 532,determined according to the type of the wiring LSI, is connected withthe pad 531. In the wiring LSI 53 shown in FIG. 12, the pad 532 a asoutput 1 is connected with the pad 531.

As shown in FIG. 13 (a), the system LSI 51 and the random number LSI 52are bonded to the wiring LSI 53. The bonding is made so that the pads514 of the system LSI 51 are connected to the pads 532 of the wiring LSI53 and the pad 522 of the random number LSI 52 is connected to the pad531 of the wiring LSI 53. Also, during the bonding, the pads 512 and 515of the system LSI 51 are connected to the ground GND.

As a result of the bonding, the random number data stored in the memorypart 521 of the random number LSI 52 is input into the random numbergeneration circuit 513 of the system LSI 51 via the wiring LSI 53 andthe input line 518 c. The random number generation circuit 513 generatesa random number to be used as the mass-production secret key based onthe random number of seed stored in the ROM 511 and the random numberdata received via the wiring LSI 53 with the logic unique to the inputline 518 c. The generated mass-production secret key is supplied to theverification section 518 via the selector 517.

When a wiring LSI 53A shown in FIG. 13 (b) in which the pad 531 isconnected with the pad 532 b is selected, the random number data storedin the memory part 521 of the random number LSI 52 is input into therandom number generation circuit 513 of the system LSI 51 via the wiringLSI 53A and the input line 518 b. Thus, the random number generationcircuit 513 generates a random number to be used as the mass-productionsecret key based on the random number of seed stored in the ROM 511 andthe random number data received via the wiring LSI 53A with the logicunique to the input line 518 b.

As described above, in this embodiment, the input line via which therandom number data is input into the random number generation circuitcan be changed by changing the type of the wiring LSI, and thus themass-production secret key can be generated with a different type oflogic.

Sixth Embodiment

The sixth embodiment of the present invention relates to testing of anLSI having a memory part from which an ID value is output according toan address supplied, using an LSI for a tester.

FIG. 14 illustrates an LSI test method of this embodiment. In FIG. 14(a), an LSI 61 includes a ROM 611 as a memory part, a first test circuit612, a comparator 613 for comparing the output of the ROM 611 with theoutput of the first test circuit 612, and a verification section 614 forprocessing using the ID value output from the ROM 611. The ROM 611stores a plurality of ID values and outputs one of the ID valuesaccording to an address supplied.

A tester LSI 62 includes a second test circuit 621, which is configuredto provide the same function as that of the ROM 611 together with thefirst test circuit 612 of the LSI 61 when they are in connection witheach other. In other words, when the first test circuit 612 receives thesame address as that supplied to the memory part 611 in the state ofbeing connected with the second test circuit 621, the first test circuit612 outputs the same value as that output from the ROM 611. FIG. 14 (b)is an example of the relationship among the address, the output of theROM 611 and the output obtained when the first and second test circuits612 and 621 are in connection with each other.

In the testing process of the LSI 61, the second test circuit 621 of thetester LSI 62 is connected to the first test circuit 612 of the LSI 61.In this state, various address values are supplied, to compare theoutput of the ROM 611 with the output of the first and second testcircuits 612 and 621 connected together.

FIGS. 15 and 16 illustrate another example of this embodiment. In FIG.15 (a), an LSI 63 includes a ROM 631 as a memory part, a first testcircuit 632, a comparator 633 for comparing the output of the ROM 631with the output of the first test circuit 632, and a verificationsection 634 for processing using the ID value output from the ROM 631.The ROM 631 stores a plurality of ID values and outputs one of the IDvalues according to an address supplied.

A tester LSI 64 includes a second test circuit 641, which is configuredto provide the same function as that of the ROM 631 together with thefirst test circuit 632 of the LSI 63 when they are in connection witheach other. FIG. 16 illustrates a specific example of configuration ofthe test circuit 641. When the first and second test circuits 632 and641 receive the same address as that supplied to the memory part 631 inthe state of connection with each other, the first test circuit 632outputs the same value as that output from the ROM 631. FIG. 15 (b) isan example of the relationship among the address, the output of the ROM631 and the output obtained when the first and second test circuits 632and 641 are in connection with each other.

In the testing process of the LSI 63, the second test circuit 641 of thetester LSI 64 is connected to the first test circuit 632 of the LSI 63.In this state, various address values are supplied, to compare theoutput of the ROM 631 with the output of the first and second testcircuits 632 and 641 connected together.

Seventh Embodiment

The seventh embodiment of the present invention relates to a developmentmethod of an encryption ID LSI obtained by bonding an encryption LSI andan ID LSI together.

FIG. 17 illustrates an encryption ID LSI of this embodiment. As shown inFIG. 17 (a), in an encryption LSI 71 as the first LSI, a development keyX is selected by a selector 711 and input into an encryption circuit712. When raw data A is input into the encryption circuit 712externally, encrypted data B encrypted with the development key X isoutput. An ID LSI 72 as the second LSI is bonded to the encryption LSI71 as shown in FIG. 17 (b), to obtain an encryption ID LSI 73. The IDLSI 72 includes a memory part 721 storing a random number R2. A randomnumber circuit 713 of the encryption LSI 71 generates a mass-productionkey Y based on a random number of seed R1 and the random number R2. Themass-production key Y generated by the random number circuit 713 variesdepending on the position N of the bonding of the ID LSI 72. Themass-production key Y is selected by the selector 711 and input into theencryption circuit 712. When the raw data A is input into the encryptioncircuit 712 externally, encrypted data C encrypted with themass-production key Y is output.

FIGS. 18 and 19 show a flowchart of the development method of theencryption ID LSI 73 shown in FIG. 17. First, referring to FIG. 18, akey publisher generates the development secret key X and the randomnumber of seed R1 (S1), and supplies them to an encryption LSI developeras the first developer (S2). The encryption LSI developer generates anencryption LSI test pattern with the development secret key X (S3), orto state differently, allows output of the encrypted data B in responseto the raw data A. The encryption LSI developer then develops theencryption LSI 71 using the supplied development secret key X (S4), andsupplies the developed encryption LSI 71 to the set developer (S5). Thekey publisher also generates a verification tester adapted to thedevelopment secret key X (S6), and supplies the verification tester tothe set developer (S7). The set developer checks the developed system(S8).

The key publisher then generates the random number R2 (S9), and suppliesthe random number R2 to an ID LSI developer as the second developer(S10). The ID LSI developer develops the ID LSI 72 using the suppliedrandom number R2 (S11) and supplies the ID LSI 72 to an encryption IDLSI producer (S12). Also, the encryption LSI developer supplies thedeveloped encryption LSI 71 to the encryption LSI producer (S13).

The key publisher determines the bonding position N (S14), and suppliesthe bonding position N to the encryption ID LSI producer (S15). Theencryption ID LSI producer bonds the encryption LSI 71 and the ID LSI 72together according to the supplied bonding position N, to therebycomplete development of the encryption ID LSI 73 (S16). The keypublisher generates the mass-production secret key Y based on the randomnumber of seed R1, the random number R2 and the bonding position N. Anyperson other than the key publisher is kept from knowing thismass-production secret key Y

Subsequently, referring to FIG. 19, the encryption ID LSI producerchecks the bonded state of the encryption ID LSI 73 (S18), and deliversa sample Z of the encryption ID LSI 73 to the set developer (S19). Thekey publisher generates a verification tester adapted to themass-production secret key Y (S19), and supplies the verification testerto the set developer (S21). The set developer checks the developedsystem (S22). After acceptance of the operation, the set developerreturns the sample Z to the encryption ID LSI producer (S23). Theencryption ID LSI producer produces a test pattern using the returnedsample Z as the reference chip (S24). That is, raw data A is input intothe sample Z and the resultant encrypted data C is used as theinput/output test pattern.

The encryption ID LSI producer mass-produces the encryption ID LSI 73(S25), conducts shipment inspection for the products using the testpattern (S26), and ships the products to the set developer (S27).

By employing the development method described above, the encryption IDLSI can be developed without the possibility that a person other thanthe key publisher may come to know the value of the mass-productionsecret key during the development.

As described above, according to the present invention, ID-installedLSIs can be mass-produced. Also, the concealment of the secret keyimproves, and the setting of the ID value and the value of the secretkey is facilitated. Moreover, the ID value installed in the LSI can betested without increase of the circuit scale. Furthermore, theconcealment of the secret key in the development process enhances.

1. An ID installable LSI comprising: a decoding section for receiving anID signal representing the ID from outside the LSI, decoding the IDsignal, and outputting the decoded signal; a value holding circuit forreceiving the decoded signal, writing the value represented by thedecoded signal therein when an operation setting signal is active, andholding the written value when the operation setting signal is inactive;and an ID memory part for storing the value held in the value holdingcircuit as the ID.
 2. The ID installable LSI of claim 1, wherein thevalue holding circuit is a fuse circuit having a nonvolatile element andthe like.
 3. The ID installable LSI of claim 1, further comprising arandom number generation circuit for receiving the value held in thevalue holding circuit and generating a random number based on thereceived value, wherein the ID memory part stores the random numbergenerated by the random number generation circuit in place of the valueheld in the value holding circuit. 4-6. (canceled)
 7. A method forinstalling a secret key in an LSI, comprising: a first step ofdetermining the position to be bumped in a pad portion of a second LSIaccording to an ID provided for a first LSI; a second step of bumpingthe position in the second LSI determined in the first step; and a thirdstep of bonding the bumped second LSI to the first LSI.
 8. (canceled) 9.An LSI test method comprising the step of: testing an LSI with a testerLSI, the LSI having a memory part from which an ID value is outputaccording to an address supplied, wherein the LSI comprises a first testcircuit, the tester LSI comprises a second test circuit, the first andsecond test circuits, in the state of being connected with each other,outputting the same value as that output from the memory part whenreceiving the same address as that supplied to the memory part, and thestep of testing comprises connecting the second test circuit of thetester LSI to the first test circuit of the LSI and comparing the outputof the connected first and second test circuits with the output of thememory part.
 10. (canceled)